Fabrication of a magnetic-tunnel-junction-based nonvolatile logic-in-memory LSI with content-aware write error masking scheme achieving 92% storage capacity and 79% power reduction

A Robust and Efficient MTJ-based Spintronic IMP Gate for New Logic Circuits and Large-Scale Integration

A novel circuit topology of a spintronic stateful implication (IMP) logic gate based on a spin transfer torqueoperated magnetic tunnel junction (STT-MTJ) is proposed and analyzed. It is demonstrated that the proposed topology reduces the IMP error and also the energy consumption by about 60% as compared to the conventional one. Stateful IMP-based logic uses the nonvolatile memory unit (MTJ devi...

Design of a Low Power Magnetic Memory in the Presence of Process Variations

With the advancement in technology and shrinkage of transistor sizes, especially in technologies below 90 nm, one of the biggest problems of the conventional CMOS circuits is the high static power consumption due to increased leakage current. Spintronic devices, like magnetic tunnel junction (MTJ), thanks to their low power consumption, non-volatility, compatibility with CMOS transistors, and t...

Perpendicular-magnetic-anisotropy CoFeB racetrack memory

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Soft/write-error-resilient CMOS/magnetic tunnel junction nonvolatile flip-flop based on majority-decision shared writing

Design of a 4-bit Non-volatile Sram Using Magnetic Tunnel Junction

In this paper, we propose a non-volatile SRAM, which presents simultaneously low power dissipation and high speed. This SRAM is based on MRAM (Magnetic RAM technology on standard CMOS. In this non-volatile SRAM design, we use Magnetic Tunnel Junctions (MTJ) as storage element. A 4-bit SRAM cell is designed and its read-write operations are described. Sense Amplifier is used in the read operatio...